Build backend flow on state-of-the-art processing node
Create SPECs for PD sign-off
Work closely with architecture and design team to optimize PPA
Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc.
Design and timing ECOs and sign-offs
任职要求：
BS or MS of EE, 5+ years of experience with the whole RTL2GDS process
Understanding the state-of-the-art of processing node, custom lib and optimizations
State-of-the-art experience with CTS and power grid planning, power integrity is a plus
Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power